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MOTOROLA
Freescale Semiconductor, Inc.
SEMICONDUCTOR TECHNICAL DATA
Order Number: MPC9259/D Rev 0, 12/2002
Preliminary Information
900 MHz Low Voltage LVDS Clock Synthesizer
MPC9259
The MPC9259 is a 3.3V compatible, PLL based clock synthesizer targeted for high performance clock generation in mid-range to high-performance telecom, networking and computing applications. With output frequencies from 50 MHz to 900 MHz and the support of differential LVDS output signals the device meets the needs of the most demanding clock applications. Features
900 MHZ LOW VOLTAGE CLOCK SYNTHESIZER
* 50 MHz to 900 MHz synthesized clock output signal
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* Differential LVDS output * LVCMOS compatible control inputs * On-chip crystal oscillator for reference frequency generation * Alternative LVCMOS compatible reference input * 3.3V power supply * Fully integrated PLL * Minimal frequency overshoot * Serial 3-wire programming interface * Parallel programming interface for power-up * 32 Pin LQFP Package * SiGe Technology * Ambient temperature range 0C to + 70 C
Functional Description The internal crystal oscillator uses the external quartz crystal as the basis of its frequency reference. The frequency of the internal crystal oscillator or external reference clock signal is multiplied by the PLL. The VCO within the PLL operates over a range of 800 to 1800 MHz. Its output is scaled by a divider that is configured by either the serial or parallel interfaces. The crystal oscillator frequency fXTAL, the PLL feedback-divider M and the PLL post-divider N determine the output frequency. The feedback path of the PLL is internal. The PLL adjusts the VCO output frequency to be M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve phase lock. The PLL will be stable if the VCO frequency is within the specified VCO frequency range (800 to 1800 MHz). The M-value must be programmed by the serial or parallel interface. The PLL post-divider N is configured through either the serial or the parallel interfaces, and can provide one of four division ratios (1, 2, 4, or 8). This divider extends performance of the part while providing a 50% duty cycle. The configuration logic has two sections: serial and parallel. The parallel interface uses the values at the M[6:0] and N[1:0] inputs to configure the internal counters. It is recommended on system reset to hold the P_LOAD input LOW until power becomes valid. On the LOW-to-HIGH transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority over the serial interface. Internal pullup resistors are provided on the M[6:0] and N[1:0] inputs prevent the LVCMOS compatible control inputs from floating. The serial interface centers on a twelve bit shift register. The shift register shifts once per rising edge of the S_CLOCK input. The serial input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this document. The configuration latches will capture the value of the shift register on the HIGH-to-LOW edge of the S_LOAD input. See the programming section for more information. The TEST output reflects various internal node values, and is controlled by the T[2:0] bits in the serial data stream. In order to minimize the PLL jitter, it is recommended to avoid active signal on the TEST output. The PWR_DOWN pin, when asserted, will synchronously divide the FOUT by 16. The power down sequence is clocked by the PLL reference clock, thereby causing the frequency reduction to happen relatively slowly. Upon de-assertion of the PWR_DOWN pin, the FOUT input will step back up to its programmed frequency in four discrete increments.
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A
(c) Motorola, Inc. 2002
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Freescale Semiconductor, Inc.
MPC9259
XTAL_IN XTAL_OUT FREF_EXT
XTAL
1 /2 0
Ref VCO
10-20 MHz
/2
PLL
800 - 1800 MHz
/1 /2 /4 /8
11 00 01 10
/16
1 OE 0 FOUT FOUT
VCC XTAL_SEL
FB
/0 to /127 7-Bit M-Divider VCC 9 M-Latch
/2 2 N-Latch
Test 3 T-Latch
TEST
P_LOAD S_LOAD
LE P/S 0 Bit 11-5 1 Bit 3-4 12 Bit Shift Register VCC 0 1 Bit 0-2
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S_DATA S_CLOCK
M[0:6] N[1:0] PWR_DOWN OE
Figure 1. MPC9259 Logic Diagram
XTAL_SEL
M[6]
M[5] 18
24 GND TEST VCC VCC GND FOUT FOUT VCC 25 26 27 28 29 30 31 32 1
23
22
21
20
19
17 16 15 14 NC M[3] M[2] M[1] M[0] P_LOAD OE XTAL_OUT
M[4] 13 12 11 10 9 8 XTAL_IN
N[1]
N[0] 3
NC
MPC9259
2
NC 4
5
6
7
PWR_DOWN
VCC_PLL
S_CLOCK
VCC_PLL
S_LOAD
Figure 2. MPC9259 32-Lead LQFP Pinout (Top View)
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FREF_EXT
S_DATA
TIMING SOLUTIONS
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MPC9259
Table 1. Pin Configuration
Pin XTAL_IN, XTAL_OUT FREF_EXT FOUT, FOUT TEST XTAL_SEL PWR_DOWN Input Output Output Input Input 1 0 0 I/O Default Type Analog LVCMOS LVDS LVCMOS LVCMOS LVCMOS Crystal oscillator interface Alternative PLL reference input Differential clock output Test and device diagnosis output PLL reference select input Configuration input for power down mode. Assertion (deassertion) of power down will decrease (increase) the output frequency by a ratio of 16 in 4 discrete steps. PWR_DOWN assertion (deassertion) is synchronous to the input reference clock. Serial configuration control input. This inputs controls the loading of the configuration latches with the contents of the shift register. The latches will be transparent when this signal is high, thus the data must be stable on the high-to-low transition. Parallel configuration control input. this input controls the loading of the configuration latches with the content of the parallel inputs (M and N). The latches will be transparent when this signal is low, thus the parallel data must be stable on the low-to-high transition of P_LOAD. P_LOAD is state sensitive. Serial configuration data input. Serial configuration clock input. Parallel configuration for PLL feedback divider (M). M is sampled on the low-to-high transition of P_LOAD. Parallel configuration for Post-PLL divider (N). N is sampled on the low-to-high transition of P_LOAD Output enable (active high) The output enable is synchronous to the output clock to eliminate the possibility of runt pulses on the FOUT output. OE = L low stops FOUT in the logic low state (FOUT = L, FOUT = H). Negative power supply (GND). Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply for correct operation. PLL positive power supply (analog power supply). Function
S_LOAD
Input
0
LVCMOS
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P_LOAD
Input
1
LVCMOS
S_DATA S_CLOCK M[0:6] N[1:0] OE
Input Input Input Input Input
0 0 1 1 1
LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS
GND VCC VCC_PLL
Supply Supply Supply
Ground VCC VCC
Table 2. Output frequency range and PLL Post-divider N PWR_DOWN 1
0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1
N 0
0 1 0 1 0 1 0 1
VCO Output f frequency di i i division
2 4 8 1 32 64 128 16
FOUT frequency range
200 - 450 MHz 100 - 225 MHz 50 - 112.5 MHz 400 - 900 MHz 12.5 - 28.125 MHz 6.25 - 14.0625 MHz 3.125 - 7.03125 MHz 25 - 56.25 MHz
TIMING SOLUTIONS
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MPC9259
Table 3. Function Table
Input XTAL_SEL OE PWR_DOWN 0 FREF_EXT Outputs disabled. FOUT is stopped in the logic low state (FOUT = L, FOUT = H) Output divider / 1 1 XTAL interface Outputs enabled Output divider /16
Table 4. General Specifications
Symbol MM HBM LU CIN Characteristics ESD protection (Machine model) ESD protection (Human body model) Latch-up immunity Input capacitance Min 200 2000 200 4.0 Typ Max Unit V V mA pF Inputs Condition
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Table 5. Absolute Maximum Ratingsa
Symbol VCC VIN VOUT IIN IOUT a Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Characteristics Min -0.3 -0.3 -0.3 Max 3.9 VCC + 0.3 VCC + 0.3 20 50 Unit V V V mA mA Condition
TS Storage temperature -65 125 C Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied.
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TIMING SOLUTIONS
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MPC9259
Table 6. DC Characteristics (VCC = 3.3V 5%, TA = 0C to + 70C)a
Symbol Characteristics Min Typ Max Unit Condition LVCMOS control inputs (FREF_EXT, PWR_DOWN, XTAL_SEL, P_LOAD, S_LOAD, S_DATA, S_CLOCK, M[0:6], N[0:1], OE) VIH VIL IIN Input high voltage Input low voltage Input Currentb 2.0 VCC + 0.3 0.8 200 V V A LVCMOS LVCMOS VIN = VCC or GND
Differential clock output FOUT VPP VOS Output Differential Voltage (peak-to-peak) Output Offset Voltage 250 1125 1275 mV mV LVDS LVDS
Test and diagnosis output TEST VOH Output High Voltage Output Low Voltage 2.0 0.55 V V IOH =-0.8 mA IOL = 0.8 mA
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VOL
Supply current ICC_PLL a. b. Maximum PLL Supply Current 20 110 mA mA VCC_PLL Pins All VCC Pins
ICC Maximum Supply Current All AC characteristics are design targets and subject to change upon device characterization. Inputs have pull-down resistors affecting the input current.
Table 7. AC Characteristics (VCC = 3.3V 5%, TA = 0C to + 70C)a
Symbol fXTAL fVCO fMAX Characteristics Crystal interface frequency range VCO frequency rangeb Output Frequency N = 11 (/1) N = 00 (/2) N = 01 (/4) N = 10 (/8) Min 10 800 400 200 100 50 0 50 45 0.05 S_DATA to S_CLOCK S_CLOCK to S_LOAD M, N to P_LOAD S_DATA to S_CLOCK M, N to P_LOAD RMS (1 )d RMS (1 ) 20 20 20 20 20 TBD TBD 25 50 55 TBD Typ Max 20 1800 900 450 225 112.5 10 Unit MHz MHz MHz MHz MHz MHz MHz ns % ns ns ns ns ns ns ps ps 20% to 80% PWR_DOWN = 0 Condition
fS_CLOCK tP,MIN DC tr, tf tS
Serial interface programming clock frequencyc Minimum pulse width Output duty cycle Output Rise/Fall Time Setup Time (S_LOAD, P_LOAD)
tS tJIT(CC) tJIT(PER) a. b. c. d.
Hold Time Cycle-to-cycle jitter Period Jitter
tLOCK Maximum PLL Lock Time 10 ms All AC characteristics are design targets and subject to change upon device characterization. The input frequency fXTAL and the PLL feedback divider M must match the VCO frequency range: fVCO = fXTAL 2 M. The frequency of S_CLOCK is limited to 10 MHz in serial programming mode. S_CLOCK can be switched at higher frequencies when used as test clock in test mode 6. See application section for more details. See application section for a jitter calculation for other confidence factors than 1 .
TIMING SOLUTIONS
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MPC9259
Table 8. MPC9259 Frequency Operating Range (in MHz)
VCO frequency for an crystal interface frequency of M 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 ... M[6:0] 0010100 0010101 0010110 0010111 0011000 0011001 0011010 0011011 0011100 0011101 0011110 0011111 0100000 0100001 0100010 0100011 0100100 0100101 0100110 0100111 0101000 0101001 0101010 0101011 0101100 0101101 0101110 0101111 0110000 0110001 0110010 0110011 0110100 0110101 0110110 0110111 0111000 0111001 0111010 0111011 0111100 0111101 0111110 0111111 1000000 800 820 840 860 880 900 920 940 960 980 1000 1020 1040 1060 1080 1100 1120 1140 1160 1180 1200 1220 1260 1260 1280 ... 816 840 864 888 912 936 960 984 1008 1032 1056 1080 1104 1128 1152 1176 1200 1224 1248 1272 1296 1320 1344 1368 1392 1416 1440 1488 1512 1512 1536 ... 812 840 875 868 896 924 952 980 1008 1036 1064 1092 1120 1148 1176 1204 1232 1260 1288 1316 1344 1372 1400 1428 1456 1484 1512 1540 1568 1596 1624 1652 1680 1736 1764 1764 1792 ... 800 832 864 896 928 960 992 1024 1056 1088 1120 1152 1184 1216 1248 1280 1312 1344 1376 1408 1440 1472 1504 1536 1568 1600 1632 1664 1696 1728 1760 1792 828 864 900 936 972 1008 1044 1080 1116 1152 1188 1224 1260 1296 1332 1368 1404 1440 1476 1512 1548 1584 1620 1656 1692 1728 1764 1800 10 MHz 12 MHz 14 MHz 16 MHz 18 MHz 20 MHz 800 840 880 920 960 1000 1040 1080 1120 1160 1200 1240 1280 1320 1360 1400 1440 1480 1520 1560 1600 1640 1680 1720 1760 1800 400 416 432 448 464 480 496 512 528 544 560 576 592 608 624 640 656 672 688 704 720 736 752 768 784 800 816 832 848 864 880 896 200 208 216 224 232 240 248 256 264 272 280 288 296 304 312 320 328 336 344 352 360 368 376 384 392 400 408 416 424 432 440 448 100 104 108 112 116 120 124 128 132 136 140 144 148 152 156 160 164 168 172 176 180 184 188 192 196 200 204 208 212 216 220 224 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 Output frequency for fXTAL=16 MHz and for N = 1 2 4 8
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TIMING SOLUTIONS
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MPC9259
Programming the MPC9259 Programming the MPC9259 amounts to properly configuring the internal PLL dividers to produce the desired synthesized frequency at the output. The output frequency can be represented by this formula: fOUT = (fXTAL / 2) (M 4) / (N 2) or fOUT = fXTAL M / N Using the parallel and serial interface The M and N counters can be loaded either through a parallel or serial interface. The parallel interface is controlled via the P_LOAD signal such that a LOW to HIGH transition will latch the information present on the M[6:0] and N[1:0] inputs into the M and N counters. When the P_LOAD signal is LOW the input latches will be transparent and any changes on the M[6:0] and N[1:0] inputs will affect the FOUT output pair. To use the serial port the S_CLOCK signal samples the information on the S_DATA line and loads it into a 12 bit shift register. Note that the P_LOAD signal must be HIGH for the serial load operation to function. The Test register is loaded with the first three bits, the N register with the next two, and the M register with the final eight bits of the data stream on the S_DATA input. For each register the most significant bit is loaded first (T2, N1 and M6). A pulse on the S_LOAD pin after the shift register is fully loaded will transfer the divide values into the counters. The HIGH to LOW transition on the S_LOAD input will latch the new divide values into the counters. Figure 3 illustrates the timing diagram for both a parallel and a serial load of the MPC9259 synthesizer. M[6:0] and N[1:0] are normally specified once at power-up through the parallel interface, and then possibly again through the serial interface. This approach allows the application to come up at one frequency and then change or fine-tune the clock as the ability to control the serial interface becomes available. Using the test and diagnosis output TEST The TEST output provides visibility for one of the several internal nodes as determined by the T[2:0] bits in the serial configuration stream. It is not configurable through the parallel interface. Although it is possible to select the node that represents FOUT, the LVCMOS output is not able to toggle fast enough for higher output frequencies and should only be used for test and dignosis. The T2, T1 and T0 control bits are preset to `000' when P_LOAD is LOW so that the PECL FOUT outputs are as jitter-free as possible. Any active signal on the TEST output pin will have detrimental affects on the jitter of the PECL output pair. In normal operations, jitter specifications are only guaranteed if the TEST output is static. The serial configuration port can be used to select one of the alternate functions for this pin. Most of the signals available on the TEST output pin are useful only for performance verification of the MPC9259 itself. However, the PLL bypass mode may be of interest at the board level for functional debug. When T[2:0] is set to 110 the MPC9259 is placed in PLL bypass mode. In this mode the S_CLOCK input is fed directly into the M and N dividers. The N divider drives the FOUT differential pair and the M counter drives the TEST output pin. In this mode the S_CLOCK input could be used for low speed board level functional test or debug. Bypassing the PLL and driving FOUT directly gives the user more control on the test clocks sent through the clocktree shows the functional setup of the PLL bypass mode. Because the S_CLOCK is a CMOS level the input frequency is limited to 200 MHz. This means the fastest the FOUT pin can be toggled via the S_CLOCK is 100 MHz as the divide ratio of the Post-PLL divider is 2 (if N = 1). Note that the M counter output on the TEST output will not be a 50% duty cycle.
(1) (2)
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where fXTAL is the crystal frequency, M is the PLL feedback-divider and N is the PLL post-divider. The input frequency and the selection of the feedback divider M is limited by the VCO-frequency range. fXTAL and M must be configured to match the VCO frequency range of 800 to 1800 MHz in order to achieve stable PLL operation: MMIN = fVCO,MIN / (2fXTAL) and MMAX = fVCO,MAX / (2fXTAL)
(3) (4)
For instance, the use of a 16 MHz input frequency requires the configuration of the PLL feedback divider between M = 25 and M = 56. Table 8 shows the usable VCO frequency and M divider range for other example input frequencies. Assuming that a 16 MHz input frequency is used, equation (2) reduces to: fOUT = 16 M / N
(5)
Substituting N for the four available values for N (1, 2, 4, 8) yields: Table 9. Output Frequency Range for fXTAL = 16 MHz N 1
0 0 1 1
FOUT Value
2 4 8 1 8M 4M 2M 16M
FOUT range
200-450 MHz 100-225 MHz 50-112.5 MHz 400-900 MHz
FOUTstep
8 MHz 4 MHz 2 MHz 16 MHz
0
0 1 0 1
Example calculation for an 16 MHz input frequency For example, if an output frequency of 384 MHz was desired, the following steps would be taken to identify the appropriate M and N values. 384 MHz falls within the frequency range set by an N value of 2, so N[1:0]=00. For N = 2, FOUT = 8M and M = FOUT/8. Therefore, M = 384 / 8 = 48, so M[6:0] = 0110000. Following this procedure a user can generate any whole frequency between 50 MHz and 900 MHz. The size of the programmable frequency steps will be equal to: fSTEP = fXTAL / N
(6)
TIMING SOLUTIONS
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MPC9259
Table 10. Test and Debug Configuration for TEST T[2:0] T2
0 0 0 0 1 1 1 1 a.
Table 11. Debug Configuration for PLL bypassa Output
FOUT S_CLOCK / N M-Counter outb TEST a. b.
TEST output T0
0 1 0 1 0 1 0 12-bit shift register outa Logic 1 fXTAL / 2 M-Counter out FOUT Logic 0 M-Counter out in PLL-bypass mode
Configuration
T1
0 0 1 1 0 0 1
T[2:0] = 110. AC specifications do not apply in PLL bypass mode Clocked out at the rate of S_CLOCK / (2N)
1 1 FOUT / 4 Clocked out at the rate of S_CLOCK
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S_CLOCK
S_DATA
T2 First Bit M, N
T1
T0
N1
N0
M6
M5
M4
M3
M2
M1
M0 Last Bit
S_LOAD M[6:0] N[1:0] P_LOAD
Figure 3. Serial Interface Timing Diagram Power Supply Filtering The MPC9259 is a mixed analog/digital product and as such it exhibits some sensitivities that would not necessarily be seen on a fully digital product. Analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. The MPC9259 provides separate power supplies for the digital circuitry (VCC) and the internal PLL (VCC_PLL) of the device. The purpose of this design technique is to try and isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a controlled environment such as an evaluation board, this level of isolation is sufficient. However, in a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simplest form of isolation is a power supply filter on the VCC_PLL pin for the MPC9259. Figure 4 illustrates a typical power supply filter scheme. The MPC9259 is most susceptible to noise with spectral content in the 1 kHz to 1 MHz range. Therefore, the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop that will be seen between the VCC supply and the MPC9259 pin of the MPC9259. From the data sheet, the VCC_PLL current (the current sourced through the VCC_PLL pin) is typically TBD mA (TBD maximum), assuming that a minimum of 3.135V must be maintained on the VCC_PLL pin, very little DC voltage drop can be tolerated when a 3.3V VCC supply is used. The resistor shown in Figure 4 must have a resistance of TBD to meet the voltage drop criteria. The RC filter pictured will provide a broadband filter with approximately 100:1 attenuation for noise whose spectral content is above 20 kHz. As the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Generally, the resistor/capacitor filter will be cheaper, easier to implement and provide an adequate level of supply filtering. A higher level of attenuation can be achieved by replacing the resistor with an appropriate valued inductor. A 1000 H choke will show a significant impedance at 10 kHz frequencies and above. Because of the current draw and the voltage that must be maintained on the VCC_PLL pin, a low DC resistance inductor is required (less than TBD ).
R1 = TBD R1 C3 = TBD F C2 = 10 nF VCC_PLL MPC9259 VCC C1 = 33...100 nF
VCC C3
Figure 4. VCC_PLL Power Supply Filter
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TIMING SOLUTIONS
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OUTLINE DIMENSIONS
FA SUFFIX LQFP PACKAGE CASE 873A-02 ISSUE A
A A1
32 25 4X
0.20 (0.008) AB T-U Z
1
-T- B
-U- V P AE
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B1
8
DETAIL Y
17
V1 AE DETAIL Y
9
-Z- 9 S1 S
4X
0.20 (0.008) AC T-U Z
G -AB-
SEATING PLANE
DETAIL AD
-AC-
BASE METAL
F
8X
M_ R
CE
SECTION AE-AE
X DETAIL AD
TIMING SOLUTIONS
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GAUGE PLANE
0.250 (0.010)
H
W
K
Q_
EE EE EE EE
N
D
0.20 (0.008)
M
AC T-U Z
0.10 (0.004) AC
NOTES: 1 DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION: MILLIMETER. 3 DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4 DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. 5 DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. 6 DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-. 7 DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8 MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9 EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.500 0.700 12_ REF 0.090 0.160 0.400 BSC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.020 0.028 12_ REF 0.004 0.006 0.016 BSC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF
J
DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X
-T-, -U-, -Z- MOTOROLA
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MPC9259
NOTES
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TIMING SOLUTIONS
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MPC9259
NOTES
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TIMING SOLUTIONS
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MPC9259
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